1. Field of the Invention
The present invention relates to a method of programming and erasing a non-volatile semiconductor memory, in particular to a method of operating the flash memory that is capable of supporting multi-level data storage with enhanced conductivity and without noise disturbance.
2. Description of Related Arts
Programming and erasing of a flash memory is usually performed by channel hot electron (CHE) or Fowler-Nordheim tunneling (FN tunneling). However, using CHE to write into memory cells usually requires excessively high power consumption. The industry has therefore developed a NAND flash memory that is operated with low power.
The structure of a memory cell (70) in a conventional NAND flash memory, as shown in FIG. 1, comprises:                a p-well (72);        an n-source (74) formed on top of the p-well (72);        an n-drain (76) formed on top of the p-well (72) corresponding to the position of the n-source (74);        a stacked gate (80), formed on the surface of the p-well (72), disposed in between the n-drain (76) and the n-source (74); wherein        The stacked gate (80) is built with a control gate (78), three successive insulation layers (82, 84, 86) of silicon oxide, silicon nitride and silicon oxide respectively, and a floating gate (88).        
The above-mentioned memory cell (70) of the NAND flash memory still has several shortcomings:
FIG. 2 shows a cross-section of the memory cells (70) of a NAND memory built in the form of a memory array, and FIG. 3 shows an equivalent circuit for the memory array (700). In the NAND flash memory, all memory cells (70) are formed on top of the same p-well (72) which is formed by an n-source (74) or an n-drain (76), and the diffusion region over the p-well is connected to a bit line (BL).
When programming a NAND memory cell, a bit line voltage (VBL) is applied over the bit line (BL), and a word line voltage (VWL) is simultaneously applied on a predetermined word line(WL) in order to induce FN tunneling for writing into a predetermined memory cell (70a). Since the selected memory cells (70a) and the non-selected memory cells (70b) are all located above a common p-well (72), the voltage applied on selected memory cells (70a) will affect other memory cells (70b) down the line sharing the same word line (WL) as a result of the FN tunnel effect. The original status of the non-selected memory cell (70b) therefore will be seriously affected. Thus, the selectivity and the efficiency of such programming/erasing operations are in question.
With reference to FIG. 4, a method of randomly programming non-volatile semiconductor memory has been proposed to solve the above-mentioned problem. One implementation of the scheme (as shown in FIG. 4) is explained hereinafter. The structure of the memory device includes:                a p-substrate (32);        a plurality of deep n-wells (34) disposed on top of the p-substrate (32);        a plurality of shallow p-wells (36) disposed in the above deep n-wells (34);        a plurality of memory cell arrays (M) created above the shallow p-wells (36);        a plurality of shallow trench insulation (STI) layers (38) disposed over the p-substrate (32) and in between the respective shallow p-wells (36), for isolating memory cell arrays (M); and        a plurality of bit lines (BL) disposed on the p-substrate (32) and extending downward to the shallow p-well (36) through a conductive plug (40).        
In the architecture of the above-mentioned memory device, the shallow p-well (36) forms a common electrode of the memory cell arrays (M). Since a shallow p-well (36) is connected to a bit line (BL) through a conductive plug (40), this design is equivalent to a buried bit line. When programming the flash memory cells, a 5V positive voltage pulse is applied on a predetermined bit line (BL), and a 10V negative voltage is simultaneously applied on the word line of the selected memory cell to create the FN tunnel effect. Since adjacent memory cell arrays (M) are isolated by the STI layer (38) in other shallow p-wells, those memory cells having the same word line (WL) as the selected memory cell will not be affected by the FN tunnel effect, thus overcoming the previously encountered problem when programming a NAND flash memory.
A new operation mode has been proposed along with the above-mentioned NAND flash memory. As shown in FIG. 5, a negative voltage is applied on the word line (WL) of a selected memory cell in the programming operation (PGM), and a positive voltage is applied on the word line (WL) of a selected memory cell in the erasing operation (ERS), in contrast to the conventional method of PGM and ERS, as shown in FIG. 6, in which a positive voltage pulse is used for PGM, whilst a negative voltage pulse is for ERS. It is noted that this operation mode can support multi-level storage on the above-mentioned flash memory.
FIG. 7 shows the distribution of a threshold voltage (Vth) for conventional flash memory cells, in which the erasing operation (ERS) is done using the negative voltage range, and the programming with multi-level storage using the positive voltage range. If the positive voltage range is provided with 1-3V for the multi-level data storage, this means there will be only a narrow pulse width allowance for each type of data stored in the same cell. It is necessary to increase the voltage range for multi-level data storage, for example using 1-5V instead of 1-3V. However, with the increased threshold voltage (Vth), the pass gate voltage (Vpass) is also increased proportionally to maintain the proper potential for the FN tunneling. However, the increased pass gate voltage (Vpass) entails more power consumption, which is obviously counter to the present design trend of low-power memory devices. The disclosure of the above-mentioned pattern application can solve the apparent dilemma.
However, since the threshold voltage (Vth) is rising gradually in relation to the erasing time, the pulse width of the threshold voltage (Vth) should be suitably restrained for the use of positive voltages in erasing, in order to avoid the concomitant increase of pass gate voltage (Vpass) along with the threshold voltage (Vth).